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NXP Semiconductors /LPC11D14 /CT32B0 /IR

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Interpret as IR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MR0Int)MR0Int 0 (MR1Int)MR1Int 0 (MR2Int)MR2Int 0 (MR3Int)MR3Int 0 (CR0Int)CR0Int 0RESERVED

Description

Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.

Fields

MR0Int

Interrupt flag for match channel 0.
MR1Int

Interrupt flag for match channel 1.
MR2Int

Interrupt flag for match channel 2.
MR3Int

Interrupt flag for match channel 3.
CR0Int

Interrupt flag for capture channel 0 event.
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data